SI/PI SIMULATION
SIGNAL AND POWER INTEGRITY

Why Signal and Power Integrity

Digital signal frequencies used on PCBs continue to rise. Now bit rates on fast serial interfaces are passing 20Gbps/lane (e.g. DP2.0, USB4). This is clearly a speed when a high-speed digital interface design becomes an RF design. This is when Signal integrity simulations and power integrity simulations play a role.

Signal integrity for signal quality

The purpose of signal integrity (SI) work is to provide a proper signal on the receiving circuit in electronics. The signal can get distortion from the non-ideal sections on the transmission line or from the coupled noise and the SI work target is to minimize these effects by electronics design

Signal quality for reliable operation

Reliable signaling within the electronics boards or between the boards leads to the absence of bit errors. Because no bit errors, no need for data resending/error correction. Therefore you can reach the following benefits: 

1. SMALLER LATENCY

Faster computing and reactions to data

2. LESS POWER CONSUMPTION

Lower maintenance costs due to longer battery life

3. NO UNKNOWN ERRORS
OR FREEZING

Customer satisfaction & reliability

Bad, small blurry eye

Good, clear open eye

Signal quality target 

A signal eye diagram is a common way to visualize the signal quality at the receiving circuit. If the signal eye is not open enough errors start to happen at receiving. The blurry signal eye demands heavy error correction and more self-awareness of the software for data corruption.

Typically, the actual signal path is the most important part of the design for signal quality. Typical design details to look into for signal integrity are:

  • Signal path lengths between differential pair
  • Printed circuit board layer stack-up structure to get proper line impedances
  • Minimize the number of vias on the signal path and make the impedance of vias as proper as possible
  • Proper grouping of signal traces on the board
  • Design the components and connectors pad areas to match the needed impedances
  • Design the possible signal components placement, pads and layout properly

Analyzing the signal integrity

The design work to estimate and analyze the signal shape and quality at the receiving circuit is called Signal Integrity (SI) analysis. One possible method is to measure the signal shape and signal eye diagram to see that the signal levels and rise/fall times are fast enough.  The measurement is not always possible because traces start & stop under the components and travel in inner layers. The simulation is the only way in these cases.

A disadvantage of this after-layout work approach is that the design is already done when you have the results. This is the reason we split the work into pre-layout and post-layout phases. In the pre-layout phase, the interesting details on the signal path are analyzed beforehand and design guides are generated for the layout designers. When the post-layout work is about analyzing the design that is already done.

Signal integrity

Signal integrity (SI) simulation
– Check and improve the performance of your high-speed PCB

We use advanced 3D EM simulation tools to improve critical portions of the high-speed lane routing, such as vias, component, and connector areas. From the simulation, the designer gets information on impedances of the routing at different locations and S-param models showing the frequency response of the transmission path. S-param model allows tuning of equalization for the path when available. We also run lower frequency (<< 5GHz) analysis showing signal waveforms which are used to tune driver strengths and terminations. This is often the case with fast clock signals and memory interfaces (e.g. SC cards and DRAMs).

Power Integrity (PI)

With power integrity analysis, power delivery network (PDN) performance is checked both for AC and DC. DC analysis ensures that enough DC power can be delivered without voltage drops and too high current densities improving also reliability. AC impedance of PDN is analyzed to meet specifications given for high performance and high current IC’s. The target here is to secure power delivery also at higher frequencies. This improves EMI levels of the processor subsystem as well.

  • S-param and TDR analysis of fast interfaces, over 20Gbps/lane supported
  • Signal waveform analysis (SI)
  • AC and DC PDN analysis (PI)

The question to consider for SI/PI:

1. Do you have a large PCB with a limited point of power? If yes, how do you know that there is a proper supply voltage to the chips?

Do you have a crowded PCB and limited space for traces?

2. How to make sure that the power lines are strong enough between the vias breaking power plane?

3. How to make sure that the signals are not disturbing each other?

4. Do you know what is the received signal quality on the chip (especially if the trace is not in a visible layer)?

5. Do you have fast and long signal interfaces, which need to be designed like transmission lines?

6. Do you have differential signals, where balance needs to be maintained?

7. Do you need to run certification analysis for memory lines (DDR4)?

We are happy to help you forward with these questions. Contact us to discuss with our expert on Power and Signal Integrity!

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