Why Signal and Power Integrity

Digital signal frequencies used on PCBs continue to rise. Now bit rates on fast serial interfaces are passing 20Gbps/lane (e.g. DP2.0, USB4). This is clearly a speed when a high-speed digital interface design becomes RF design.

The question to consider for SI/PI:

1. Do you have a large PCB with a limited point of power? If yes, how do you know that there is a proper supply voltage to the chips?

Power Integrity

Do you have a crowded PCB and limited space for traces?

2. How to make sure that the power lines are strong enough between the vias breaking power plane?

Power Integrity

3. How to make sure that the signals are not disturbing each other?

Signal Integrity

4. Do you know what is the received signal quality on the chip (especially if the trace is not in a visible layer)?

Signal Integrity

5. Do you have fast and long signal interfaces, which need to be designed like transmission lines?

Signal Integrity

6. Do you have differential signals, where balance needs to be maintained?

Signal Integrity

7. Do you need to run certification analysis for memory lines (DDR4)?

Signal Integrity

We are happy to help you forward with these questions. Contact us to discuss with our expert on Power and Signal Integrity!

Signal integrity

Signal integrity (SI) – Check and improve performance of your high-speed PCB

We use advanced 3D EM simulation tools to improve critical portions of the high-speed lane routing, such as vias, component, and connector areas. From the simulation, the designer gets information on impedances of the routing at different locations and S-param models showing the frequency response of the transmission path. S-param model allows tuning of equalization for the path when available. We also run lower frequency (<< 5GHz) analysis showing signal waveforms which are used to tune driver strengths and terminations. This is often the case with fast clock signals and memory interfaces (e.g. SC cards and DRAMs).

Power Integrity (PI)

With power integrity analysis, power delivery network (PDN) performance is checked both for AC and DC. DC analysis ensures that enough DC power can be delivered without voltage drops and too high current densities improving also reliability. AC impedance of PDN is analyzed to meet specifications given for high performance and high current IC’s. The target here is to secure power delivery also at higher frequencies. This improves EMI levels of the processor subsystem as well.

  • S-param and TDR analysis of fast interfaces, over 20Gbps/lane supported
  • Signal waveform analysis (SI)
  • AC and DC PDN analysis (PI)

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